Regviz

Silicon Labs /BGM220PC22WGA /ICACHE0_S /LPMODE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LPMODE

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/ICACHE0_S/LPMODE#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BASIC)LPLEVEL 0NESTFACTOR

LPLEVEL=BASIC

Description

No Description

Fields

LPLEVEL

Low Power Level

0 (BASIC): Base instruction cache functionality

1 (ADVANCED): Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory

3 (MINACTIVITY): Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality.
NESTFACTOR

Low Power Nest Factor

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data